----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:52:31 03/14/2012 
-- Design Name: 
-- Module Name:    Uartverwerking - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Uartverwerking is
    Port ( clk_50MHz : in  STD_LOGIC;
				done : in std_logic;
				reset_parity : out std_logic;
           READ_RAM16x8data : in  STD_LOGIC_VECTOR (7 downto 0);
           READ_RAM16x8addr : out  STD_LOGIC_VECTOR (3 downto 0);
           Write_idram_en : out  STD_LOGIC;
           write_idram_data : out  STD_LOGIC_VECTOR (5 downto 0);
           Write_idram_addr : out  STD_LOGIC_VECTOR (7 downto 0));
end Uartverwerking;

architecture Behavioral of Uartverwerking is

signal signals : std_logic_vector (4 downto 0) := "00000";
signal addr_temp : integer;
signal addr_temp_int : integer;
signal write_idram_data_sig : std_logic_vector (7 downto 0);
signal clk_25MHz : std_logic;
signal latch : std_logic;


begin
write_idram_data <= write_idram_data_sig (5 downto 0);


--process(done)
--begin
--if done = '1' then
--	null;
--	else
--	signals <= "00000";
--end if;
--
--end process;
DELER: process (clk_50Mhz)
begin
if rising_edge(clk_50MHz) then
	if clk_25Mhz = '1' then clk_25MHz <= '0';
	else clk_25MHz <= '1';
	end if;
end if;
end process;



process (clk_25MHz)
begin

if rising_edge(clk_25MHz) then
	if done = '1' then
		latch <= '1';
		reset_parity <= '1';
	end if;
	if latch = '1' then
		CASE signals IS
			WHEN  "00000"  =>  READ_RAM16x8addr <= "0001"; -- adres locatie in ram
										signals <= "01110";
			WHEN  "01110" =>  READ_RAM16x8addr <= "0001"; -- adres locatie in ram
										reset_parity <= '0';
										signals <= "00001";
			WHEN  "00001"  =>  addr_temp <= to_integer(unsigned(READ_RAM16x8data));
										signals <= "00010";
										READ_RAM16x8addr <= "0011"; -- eerste databyte in ram
										
	-- eerste byte wegschrijvein									
			WHEN  "00010"  =>    Write_idram_data_sig	<= READ_RAM16x8data;
										READ_RAM16x8addr <= "0100"; --  databyte in ram
										Write_idram_en <= '1';
										--addr_temp <= addr_temp+1; -- tel 1 op bij addr_temp
										signals <= "00011";
	-- 2de byte wegschrijven
			WHEN  "00011"  =>    write_idram_data_sig	<= READ_RAM16x8data;
										READ_RAM16x8addr <= "0101"; --  databyte in ram
										
										addr_temp <= addr_temp+1; -- tel 1 op bij addr_temp
										signals <= "00100";
	-- 3de byte wegschrijven
			WHEN  "00100"  =>    write_idram_data_sig	<= READ_RAM16x8data;
										READ_RAM16x8addr <= "0110"; --  databyte in ram
										
										addr_temp <= addr_temp+1; -- tel 1 op bij addr_temp
										signals <= "00101";
	-- 4de byte wegschrijven									
			WHEN  "00101"  =>    write_idram_data_sig	<= READ_RAM16x8data;
											READ_RAM16x8addr <= "0111"; --  databyte in ram
									
										addr_temp <= addr_temp+1; -- tel 1 op bij addr_temp
										signals <= "00110";
	--5de byte wegschrijven
			WHEN  "00110"  =>    write_idram_data_sig	<= READ_RAM16x8data;
										READ_RAM16x8addr <= "1000"; --  databyte in ram
										
										addr_temp <= addr_temp+1; -- tel 1 op bij addr_temp
										signals <= "00111";
	-- 6de byte wegschrijven
			WHEN  "00111"  =>    write_idram_data_sig	<= READ_RAM16x8data;
										READ_RAM16x8addr <= "1001"; --  databyte in ram
										
										addr_temp <= addr_temp+1; -- tel 1 op bij addr_temp
										signals <= "01000";
	-- 7de byte wegschrijven
			WHEN  "01000"  =>    write_idram_data_sig	<= READ_RAM16x8data;
										READ_RAM16x8addr <= "1010"; --  databyte in ram
										
										addr_temp <= addr_temp+1; -- tel 1 op bij addr_temp
										signals <= "01001";
	-- 8ste byte wegschrijven
			WHEN  "01001"  =>    write_idram_data_sig	<= READ_RAM16x8data;
										READ_RAM16x8addr <= "1011"; --  databyte in ram
										
										addr_temp <= addr_temp+1; -- tel 1 op bij addr_temp
										signals <= "01010";
	-- 9de
			WHEN  "01010"  =>    write_idram_data_sig	<= READ_RAM16x8data;
										READ_RAM16x8addr <= "1100"; --  databyte in ram
										
										addr_temp <= addr_temp+1; -- tel 1 op bij addr_temp
										signals <= "01011";
	-- 10de
			WHEN  "01011"  =>    write_idram_data_sig	<= READ_RAM16x8data;
										
										addr_temp <= addr_temp+1; -- tel 1 op bij addr_temp
										signals <= "01100";
			WHEN  "01100"  =>    write_idram_data_sig	<= READ_RAM16x8data;
										
										--addr_temp <= addr_temp+1; -- tel 1 op bij addr_temp
										signals <= "01101";


			WHEN OTHERS 	=>  	signals <= "00000";
										addr_temp <= 0;
										write_idram_en <= '0';
										READ_RAM16x8addr <= "0001";
										reset_parity <= '1';
										latch <= '0';
										
		END CASE;
	else signals <= "00000";
	reset_parity <= '0';
	end if;
end if;
end process;

write_idram_addr <= std_logic_vector(to_unsigned(addr_temp,8));
  
end Behavioral;

library ieee;
use ieee.std_logic_1164.all;

package ramtoram is 

	COMPONENT Uartverwerking
	PORT(
		clk_50MHz : IN std_logic;
		done : IN std_logic;
		reset_parity : out std_logic;
		READ_RAM16x8data : IN std_logic_vector(7 downto 0);          
		READ_RAM16x8addr : OUT std_logic_vector(3 downto 0);
		Write_idram_en : OUT std_logic;
		write_idram_data : OUT std_logic_vector(5 downto 0);
		Write_idram_addr : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;
	
end package;